Breaking Taps Designed a Working Silicon Chip and Got It Back Alive

Zachary Tong had never designed a chip. He had never programmed an FPGA either, and he will tell you his electrical skills were rough. With about a month left before the first wafer.space deadline, he still decided to write a microprocessor, send the file to a real foundry, and wait to see if silicon came back alive.

After researching old processor ideas, he eventually settled on Transport Triggered Architecture, an unusual choice. A normal chip is told to add one register to another and store the result. BreakingTTAPs mostly moves data. You enter a value into a port on a functional unit, and the operation occurs when the data arrives. He has two 32-bit busses side by side, so he can complete two of those moves in a single clock cycle, which is effectively enough to qualify as superscalar in today’s terms.

The clock speed is in the 18-20 megahertz range. Program memory featured 1,024 slots, each with two instructions, plus 256 words of stack and 4 kilobytes of general purpose RAM. There are approximately 80 operations spread among 20-30 functional units, including branches, comparisons, math, bitwise operations, and a random number generator for good measure. The pin headers provide sixteen general-purpose inputs and sixteen outputs, as well as an 8-bit parallel boot channel for loading programs. Unfortunately, his SPI is dead on the die, and the UART is a write-off; nevertheless, it may still be recovered.

One specific section of code is a huge pain in the neck since a multiply-and-accumulate unit took up a significant amount of space on the die and fouled up the timing. Tong was still new to this type of stuff, so he didn’t feel comfortable digging into the failure all the way to the bottom of it, thus the clock speed target remained a fight until the file had to be pushed out the door. He developed the logic in Spade, a hardware language he is also learning on the side, and then used open-source tools to arrange the transistors and draw the cables. The handoff process is also rather stringent, as the foundry expects a clean GDS file, and any minor errors in it become permanent as soon as the wafer begins rolling.

Wafer.space, run by Tim out of Singapore, is the shuttle that made the order possible. The designs are printed onto a single reticle on a GlobalFoundries 180 nm wafer using the GF180MCU mixed-signal process. Every time it prints, we receive a wafer with approximately a thousand dies on it after 3-4 months in the oven. Older geometry implies that the silicon is quite large by today’s standards. Unlike a Tiny Tapeout tile, this die contains only one circuit. The bundled parts we received revealed the real chip underneath, which was viewable via clear epoxy and ready to be inserted into the socket.

Bring-up was the short path, not the careful one. A carrier is slapped into a breadboard, a Raspberry Pi Pico starts up and loads a program, and the chip just counts up to 100 before shutting down. That was the proof in a single loop, with no bother. SPI failed just as expected, according to the debugging. The code for the Spade version, as well as the produced Verilog, are all publicly available, and Tong has even been distributing finished BreakingTTAPs boards to anyone who wants to experiment with one on their bench.

The second design is named BTX. That one is already in the foundry line. It’s a special processor designed specifically for ray tracing, with a completely new graphics system planned for it. Spaces on the shuttle are still available for anyone wishing to create their own chip, as you can purchase a slice of the wafer for a few thousand dollars for a thousand dies, with files expected in December 2026.